View AD1981BJST-REEL_443892.PDF datasheet online --- IC-ON-LINE

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FEATURES AC '97 2.3 COMPATIBLE FEATURES S/PDIF Output, 20 Bits Data Format, Supporting 48 kHz and 44.1 kHz Sample Rates Integrated Stereo Headphone Amplifier Variable Sample Rate Audio External Audio Power-Down Control Greater than 90 dB Dynamic Range Stereo Full-Duplex Codec 20-Bit PCM DAC 3 Analog Line-Level Stereo Inputs for Line-In, AUX, and CD Mono Line-Level Phone Input Dual MIC Input with Built-In Programmable Preamp High Quality CD Input with Ground Sense
AC '97 SoundMAX Codec AD1981B
Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Lead LQFP Package, Lead-Free Available ENHANCED FEATURES Stereo MIC Preamps Support Built-In Digital Equalizer Function for Optimized Speaker Sound Full-Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software Programmed VREFOUT Output for Biasing Microphone and External Power Amp Split Power Supplies: 3.3 V Digital and 5 V Analog Multiple Codec Configuration Options
(R)
FUNCTIONAL BLOCK DIAGRAM
VREFOUT VREF XTL_OUT XTL_IN SPDIF
AD1981B
G MIC PREAMP MIC1
MS
VOLTAGE REFERENCE
CODEC CORE
G G
2CMIC
SPDIF TX
MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R CD DIFF AMP
PCM L/R ADC RATE
RECORD SELECTOR
PLL
ID0
G
M
16-BIT - ADC 16-BIT - ADC ID1
G
M
G G MONO_OUT M A
MIX
M M
16-BIT - ADC 16-BIT - ADC
AC '97 INTERFACE
ADC AND DAC SLOT LOGIC
RESET
SYNC
BIT_CLK
EQ CORE STORAGE
M
GA
20-BIT - DAC
BYPASS
SDATA_OUT
EQ
HP_OUT_L
HP
M
A
OUTPUT SELECTOR
M GA GA M M M M GA GA GA GA M M M M M GA GA
GA
20-BIT - DAC PCM FRONT DAC RATE
BYPASS
SDATA_IN
EQ
LINE_OUT_L
MZ
A
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
LINE_OUT_R
MZ
A
AC '97 CONTROL REGISTERS
HP_OUT_R
HP
M
A M
ANALOG MIXING CONTROL LOGIC
EAPD
JS0
JS1
EAPD
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD1981B-SPECIFICATIONS
STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED DAC Test Conditions
Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (FS) Input Signal Analog Output Pass Band
25C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz
Calibrated -3 dB Attenuation Relative to Full Scale 0 dB Input 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT)
ADC Test Conditions
Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale
Parameter ANALOG INPUT Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, PHONE_IN MIC_IN with +20 dB Gain MIC_IN with 0 dB Gain Input Impedance1 Input Capacitance1 MASTER VOLUME Step Size (0 dB to -46.5 dB): LINE_OUT_L, LINE_OUT_R Output Attenuation Range1 Step Size (0 dB to -46.5 dB): MONO_OUT Output Attenuation Range1 Step Size (0 dB to -46.5 dB): HP_OUT_R, HP_OUT_L Output Attenuation Range Span1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT1 Step Size (+12 dB to -34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
1
Min
Typ
Max
Unit
1 2.83 0.1 0.283 1 2.83 20 5 1.5 46.5 1.5 46.5 1.5 46.5 80 1.5 22.5
7.5
V rms V p-p V rms V p-p V rms V p-p k pF dB dB dB dB dB dB dB dB dB
90 90 1.5 46.5 0 0.4 0.6 -74 fS fS 16/fS 0 0.4 fS 0.09 0.6 fS
dB dB dB dB Hz dB Hz Hz dB sec s
-2-
REV. B
AD1981B
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1 (CCIF Method) ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line_In to Other Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1 (CCIF Method) Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy1 (Measured from 0.6 fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance1 VREF VREF_OUT (Programmable to 3.70 V Nominal) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range--Analog (AVDD) Power Supply Range--Digital (DVDD) Power Dissipation--5 V/3.3 V Analog Supply Current--5 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) Min Typ 16 -84 85 85 -80 -100 Max Unit Bits dB dB dB dB dB % dB mV Bits dB dB dB dB % dB dB dB V rms V p-p k pF pF V rms V V mA mV V V V V A A V V mW mA mA dB
80
-80 10 0.5 5
85
20 -85 -75 90 -100 10
0.7 -80
-40 1 2.83 800 10 15 100 1 32 2.05 2.25 2.25 5 0.65 0.9 -10 -10 4.5 3.0 400 50 46 40 DVDD 0.35 DVDD 0.1 DVDD +10 +10 5.5 3.47 DVDD 2.45 5
REV. B
-3-
AD1981B SPECIFICATIONS (continued)
Parameter CLOCK SPECIFICATIONS Input Clock Frequency Recommended Clock Duty Cycle
NOTES 1 Guaranteed but not tested. 2 Measurements reflect main ADC. Specifications subject to change without notice.
1
Min
Typ 24.576 50
Max
Unit MHz %
40
60
Parameter POWER-DOWN STATES* (Fully Active) ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby
*Values presented with V REFOUT not loaded. Specifications subject to change without notice.
Set Bits (No Bits Value) PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 42 36 29 12 42 36 29 12 0 42
AVDD Typ 51 45 35 28 24 18 9 1.5 0 44
Unit mA mA mA mA mA mA mA mA mA mA
TIMING PARAMETERS
Parameter
(Guaranteed over Operating Temperature Range)
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF 32.56 32.56 5 5 2 2 2 2 2 2 2 2 0 15 25 15 50 15 Min 162.8 1.3 19.5 162.8 12.288 81.4 750 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 1 2000 48.84 Typ 1.0 Max Unit ms ns ms s ns MHz ppm ns ps ns ns kHz ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2, 3 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to Hi-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
6 6 6 6 6 6 6 6 1.0
NOTES 1 Guaranteed but not tested. 2 Output jitter is directly dependent on crystal input jitter. 3 Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower. Specifications subject to change without notice.
-4-
REV. B
AD1981B
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 1. Cold Reset Timing (Codec Is Supplying the BIT_CLK Signal)
tSYNC_HIGH
SYNC
tSYNC2CLK
BIT_CLK
Figure 2. Warm Reset Timing
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD tSYNC_LOW
SYNC
tSYNC_HIGH tSYNC_PERIOD
Figure 3. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
SYNC
tRISESYNC
tFALLSYNC
SDATA_IN
tRISEDIN
tFALLDIN
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 4. Signal Rise and Fall Times
REV. B
-5-
AD1981B
SLOT 1 SYNC
SLOT 2
BIT_CLK
SDATA_OUT
WRITE TO 0x20
DATA PR4
tS2_PDOWN
SDATA_IN BIT_CLK NOT TO SCALE
Figure 5. AC-Link Low Power Mode Timing
tCO tSETUP
VIH
BIT_CLK
VIL
SDATA_O SDATA_I SYNC VOH VOL
tHOLD
Figure 6. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
RESET
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O Hi-Z
tOFF
Figure 7. ATE Test Mode
-6-
REV. B
AD1981B
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
ENVIRONMENTAL CONDITIONS*
Power Supplies Digital (DVDD) . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V Analog (AVDD) . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6.0 V Input Current (Except Supply Pins) . . . . . . . . . . . . . . 10 mA Signals Pins Digital Input Voltage . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V Analog Input Voltage . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Ambient Temperature Range (Operating) . . . . . . . 0C to 70C
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating (LQFP Package) TCASE = Case Temperature in C PD = Power Dissipation in W JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Package LQFP
JA JC
50.1C/W
17.8C/W
*All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7
ORDERING GUIDE
Model AD1981BJST AD1981BJST-REEL AD1981BJSTZ2 AD1981BJSTZ-REEL2
1 2
Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C
Package Description 48-Lead LQFP (Tray) 48-Lead LQFP (Reel) 48-Lead LQFP (Tray) 48-Lead LQFP (Reel)
Package Option1 ST-48 ST-48 ST-48 ST-48
ST = Low Profile Quad Flatpack. The AD1981BJSTZ is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure tin electroplate. The device is suitable for lead-free applications and is able to withstand surface-mount soldering at up to 255 C ( 5C). In addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-lead solder pastes at reflow temperatures of 220C to 235C.
PIN CONFIGURATION 48-Lead LQFP
MONO_OUT
37 36 LINE_OUT_R 35 LINE_OUT_L 34 AVDD4 33 AVSS4 32 AFILT4 31 AFILT3 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1
HP_OUT_R
HP_OUT_L
39
AVDD3
AVSS3
SPDIF
EAPD
ID1
ID0
48
47
46
45
44
43
42
41
40
AVSS2
NC
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12
AD1981B
TOP VIEW (Not to Scale)
PHONE_IN 13
AUX_L 14
AUX_R 15
JS1 16
JS0 17
CD_L 18
CD_GND_REF 19
CD_R 20
MIC1 21
MIC2 22
LINE_IN_L 23
38
AVDD2
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1981B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
-7-
LINE_IN_R 24
AD1981B
PIN FUNCTION DESCRIPTIONS
Pin No.
DIGITAL I/O 2 3 5 6 8 10 11 48
Mnemonic
XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF ID0 ID1
I/O
I O I O/I O I I O
Function
Crystal Input (24.576 MHz) or External Clock Input. Crystal Output. AC-Link Serial Data Output, AD1981B Data Input Stream. AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input if Secondary Mode Selected. AC-Link Serial Data Input, AD1981B Data Output Stream. AC-Link Frame Sync. AC-Link Reset, AD1981B Master Hardware Reset. S/PDIF Output.
CHIP SELECTS (These pins can also be used to select an external clock. See Table IX.) 45 46 I I Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary codec. Chip Select Input 1 (Active Low).
JACK SENSE AND EAPD 17 16 47 ANALOG I/O 13 14 15 18 19 20 21 22 23 24 35 36 37 39 41 PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R I I I I I I I I I I O O O O O Phone Input. Mono input from telephony subsystem speaker phone or handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode Selected (Stereo MIC). Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode Selected (Stereo MIC). Line In Left Channel. Line In Right Channel. Line Out (Front) Left Channel. Line Out (Front) Right Channel. Monaural Output to Telephony Subsystem Speakerphone. Headphone Left Channel Output. Headphone Right Channel Output. JS0 JS1 EAPD I I O Jack Sense 0 Input. Jack Sense 1 Input. External Amp Power-Down Control.
FILTER/REFERENCE (These signals are connected to resistors, capacitors, or specific voltages.) 27 28 29 30 31 32 VREF VREFOUT AFILT1 AFILT2 AFILT3 AFILT4 O O O O O O Voltage Reference Filter. Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. Antialiasing Filter Capacitor--Mixer ADC Right Channel. Antialiasing Filter Capacitor--Mixer ADC Left Channel.
POWER AND GROUND SIGNALS 1 4 7 9 25 26 38 40 43 44 34 33 NO CONNECTS 12 42 NC NC No Connect. No Connect. DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 AVDD4 AVSS4 I I I I I I I I I I I I Digital VDD 3.3 V. Digital GND. Digital GND. Digital VDD 3.3 V. Analog VDD 5.0 V. Analog GND. Analog VDD 5.0 V. Analog GND. Analog VDD 5.0 V. Analog GND. Analog VDD 5.0 V. Analog GND.
-8-
REV. B
AD1981B
Indexed Control Registers
Reg Name 00h 02h 04h 06h Reset Master Volume Headphones Volume Mono Volume D15 X MM HPM MVM PHM MCM LVM CVM AM OM X IM X EAPD IDC1 D14 SE4 X X X X X X X X X X X X PR6 IDC0 D13 SE3 X X X X X X X X X X X X PR5 X X D12 SE2 LMV4 LHV4 X X X LLV4 LCV4 LAV4 LOV4 X X X PR4 X X D11 SE1 LMV3 LHV3 X X X LLV3 LCV3 LAV3 LOV3 X LIM3 X PR3 D10 SE0 LMV2 LHV2 X X X LLV2 LCV2 LAV2 LOV2 LS2 LIM2 X PR2 D9 ID9 D8 ID8 D7 ID7 D6 ID6 X X X X M20 X X X X X X D5 ID5 X X X X X X X X X X X X X D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0090h 8000h 8000h 8000h 8008h
LMV1 LMV0 RM* LHV1 LHV0 RM* X X X X X X X X X
RMV4 RMV3 RMV2 RMV1 RMV0 RHV4 RHV3 RHV2 RHV1 RHV0 MV4 MV3 MV2 MV1 MV0
0Ch Phone Volume 0Eh 10h 12h 16h 18h MIC Volume Line-In Volume CD Volume AUX Volume PCM-Out Vol
PHV4 PHV3 PHV2 PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h RLV4 RLV3 RLV2 RLV1 RLV0 RCV4 RCV3 RCV2 RCV1 RCV0 RAV4 RAV3 RAV2 RAV1 RAV0 ROV4 ROV3 ROV2 ROV1 ROV0 X X X X X RS2 RS1 RS0 8808h 8808h 8808h 8808h 0000h 8000h 0000h 000Xh X605h 0000h BB80h BB80h 2000h 8080h 0000h
LLV1 LLV0 RM* LCV1 LCV0 RM* LAV1 LAV0 RM* LOV1 LOV0 RM* LS1 LS0 X
1Ah Record Select 1Ch Record Gain 20h 26h 28h General-Purpose Power-Down Ctrl/Stat Ext'd Audio ID
LIM1 LIM0 RM* MIX PR1 MS PR0
RIM3 RIM2 RIM1 RIM0 X REF X ANL X DAC X ADC VRAS VRA SRF0
LPBK X X X X SRF7 X X X SRF6
REVC1 REVC0 AMAP X X SPCV X X SRF8
DSA1 DSA0 X SPSA1 SPSA0 X SRF5 SRF4 SRF3
SPDIF X SPDIF X SRF2 SRF1
2Ah Ext'd Audio Stat/ VFORCE X Ctrl 2Ch PCM Front DAC Rate 32h PCM L/R ADC Rate SRF15 SRA15 V EQM CFD15 MXM X SLOT 16 DACZ F7 T7
SRF14 SRF13 SRA14 SRA13 X MAD LBEN SPSR1 X
SRF12 SRF11 SRF10 SRF9
SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SPSR0 L X X CC6 X CC5 X CC4 X CC3 SYM CC2 CHS
SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 CC1 CC0 PRE COPY /AUD PRO
3Ah SPDIF Control 60h 62h 64h 72h 74h 76h EQ CTRL EQ DATA Mixer ADC, Volume Jack Sense Serial Configuration Misc Control Bits
BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 X JS1 MD X X JS0 MD INTS MAD ST S4
CFD14 CFD13 X X X X
CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 X JS MT2 LMG3 LMG2 LMG1 LMG0 RM* JS MT1 JS MT0 X X F2 T2 JS1 EQB X JS0 EQB JS1 TMR X JS0 TMR X
RMG3 RMG2 RMG1 RMG0 8000h JS1 ST X JS0 ST JS1 INT JS0 INT 0000h
REGM REGM 2 1 X F6 T6 M SPLT F5 T5
REGM X 0 LODIS DAM F4 T4 F3 T3
CHEN X MAD PD S7
SPAL SPDZ SPLNK 7001h
FMXE X F1 T1 F0 T0
2CMIC X S6 S5
VREF VREF MBG1 MBG0 0000h H D S3 S2 S1 S0 4144h 5374h
7Ch Vendor ID1 7Eh Vendor ID2
REV7 REV6
REV5 REV4 REV3 REV2 REV1 REV0
NOTES All registers not shown. Bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *For AC '97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
REV. B
-9-
AD1981B
Reset Register (Index 00h)
Reg No. 00h Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0090h
NOTES X in the above table is a wild card and has no effect on the value. Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following: Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated Mic PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1981B 0 0 0 0 1 0 0 1 0 0
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).
Master Volume Register (Index 02h)
Reg No. 02h
Name Master Volume
D15
D14
D13 X
D12
D11
D10
D9
D8
D7
D6
D5 X
D4
D3
D2
D1
D0
Default
MM X
LMV4 LMV3 LMV2 LMV1 LMV0 RM* X
RMV4 RMV3 RMV2 RMV1 RMV0 8000h
* For AC `97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1. RMV[4:0] RM LMV[4:0] MM Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Master Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
-10-
REV. B
AD1981B
Headphones Volume Register (Index 04h)
Reg No. Name D15 D14 D13 X D12 LHV 4 D11 LHV 3 D10 LHV 2 D9 LHV 1 D8 LHV 0 D7 RM* D6 X D5 X D4 RHV 4 D3 RHV 3 D2 RHV 2 D1 RHV 1 D0 RHV 0 Default 8000h
04h Headphone HPM X Volume
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the headphone volume controls for both stereo channels and mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1. RHV [4:0] RM LHV [4:0] HPM Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the HPM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Headphones Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table I. Volume Settings for Master and Headphone
Reg. 76h MSPLT* 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 D15 WRITE 00 0000 00 1111 01 1111 1x xxxx xx xxxx 1x xxxx xx xxxx xx xxxx
Control Bits Master Volume (02h) and Headphone Volume (04h) Left Channel Volume D[13:8] READBACK Function 00 0000 00 1111 01 1111 01 1111 xx xxxx 01 1111 xx xxxx xx xxxx 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted -46.5 dB Gain - dB Gain, Left Only Muted - dB Gain, Left Muted D7* x x x x x 1 0 1 Right Channel Volume D[5:0] WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx xx xxxx xx xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx xx xxxx xx xxxx xx xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted -46.5 dB Gain - dB Gain, Right Muted
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. X in the above table is a wild card and has no effect on the value.
REV. B
-11-
AD1981B
Mono Volume Register (Index 06h)
Reg No. Name 06h D15 D14 D13 X X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 MV4 D3 MV3 D2 MV2 D1 MV1 D0 MV0 Default 8000h
Mono Volume MVM
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table II for examples. This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1.
MV[4:0] MVM
Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Mono Volume Mute. When this bit is set to 1, the channel is muted.
Table II. Volume Settings for Mono
Control Bits D[4:0] for Mono (06h) D15 0 0 0 1 WRITE 0000 0 1111 1 1111 x xxxx READBACK 0 0000 0 1111 1 1111 x xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain - dB Gain, Muted
x in the above table is a wild card and has no effect on the value.
Phone Volume Register (Index 0Ch)
Reg No. Name 0Ch Phone Volume D15 PHM D14 D13 X X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PHV4 D3 PHV3 D2 PHV2 D1 D0 Default 8008h
PHV1 PHV0
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
PHV[4:0] PHM
Phone Volume. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. Phone Mute. When this bit is set to 1, the phone channel is muted.
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
-12-
REV. B
AD1981B
MIC Volume Register (Index 0Eh)
Reg No. Name 0Eh MIC Volume D15 D14 D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 M20 D5 X D4 MCV4 D3 MCV3 D2 MCV2 D1 D0 Default
MCM X
MCV1 MCV0 8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
MCV[4:0]
MIC Volume Gain. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB; however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 dB or 30 dB if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1) MIC Mute. When this bit is set to 1, the MIC channel is muted.
M20
MCM
Table III. Volume Settings for Phone and MIC
Control Bits D[4:0] Phone (0Ch) and Mic (0Eh) D15 0 0 0 1 WRITE 0 0000 0 1000 1 1111 x xxxx READBACK 0 0000 0 1000 1 1111 x xxxx Function 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted
x in the above table is a wild card, and has no effect on the value.
Line-In Volume Register (Index 10h)
Reg No. Name D15 D14 D13 D12 X X D11 D10 LLV2 D9 D8 D7 D6 D5 X D4 RLV4 D3 RLV3 D2 D1 D0 Default
10h Line-In Volume LVM
LLV4 LLV3
LLV1 LLV0 RM* X
RLV2 RLV1 RLV0 8808h
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RLV[4:0] RM LLV[4:0] LVM
Line In Volume Right. Allows setting the line-in right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the LM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Line In Volume Left. Allows setting the line in left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
REV. B
-13-
AD1981B
CD Volume Register (Index 12h)
Reg No. Name 12h CD Volume D15 D14 D13 D12 X D11 D10 D9 D8 D7 D6 D5 X D4 RCV4 D3 RCV3 D2 D1 D0 Default
CVM X
LCV4 LCV3 LCV2 LCV1 LCV0 RM* X
RCV2 RCV1 RCV0 8808h
*For AC '97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RCV[4:0] RM LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the CVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
AUX Volume Register (Index 16h)
Reg No. Name 16h AUX Volume
D15 AM
D14 X
D13 D12 X
D11
D10
D9
D8
D7
D6
D5 X
D4 RAV4
D3
D2
D1
D0
Default
LAV4 LAV3 LAV2
LAV1 LAV0 RM* X
RAV3 RAV2 RAV1 RAV0 8808h
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RAV[4:0] RM LAV[4:0] AM
Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left AUX Volume. Allows setting the AUX left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. AUX Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
PCM-Out Volume Register (Index 18h)
Reg No. Name
D15 D14 D13 D12 X
D11
D10
D9
D8
D7
D6
D5 X
D4
D3
D2
D1
D0
Default
18h PCM-Out Volume OM X
LOV4 LOV3 LOV2
LOV1 LOV0 RM* X
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
ROV[4:0] RM LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the OM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
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REV. B
AD1981B
Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Reg. 76h
Control Bits Line-In (10h), CD (12h), AUX (16h), and PCM-Out (18h) Left Channel Volume D[12:8] Right Channel Volume D[4:0] D7* WRITE x x x x 1 0 0000 0 1000 1 1111 x xxxx x xxxx 1 1111 x xxxx READBACK Function 0 0000 0 1000 1 1111 x xxxx x xxxx 1 1111 x xxxx +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted -34.5 dB Gain - dB Gain, Right Muted
MSPLT* D15 WRITE READBACK Function 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx 12 dB Gain 0 dB Gain 34.5 dB Gain - dB Gain, Muted -34.5 dB Gain
- dB Gain, 0 Left Only Muted - dB Gain, Left Muted 1
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. x in the above table is a wild card and has no effect on the value.
Record Select Control Register (Index 1Ah)
Reg No. Name 1Ah Record Select D15 X D14 X D13 X D12 X D11 X D10 LS2 D9 LS1 D8 LS0 D7 X D6 X D5 X D4 X D3 X D2 RS2 D1 RS1 D0 RS0 Default 0000h
All registers not shown and bits containing an X are assumed to be reserved. Used to select the record source independently for right and left. The default value is 0000h, which corresponds to MIC In. Refer to Table V for examples.
RS[2:0] LS[2:0]
Right Record Select Left Record Select
Table V. Settings for Record Select Control
LS [10:8] 000 001 010 011 100 101 110 111
Left Record Source MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN
RS [2:0] 000 001 010 011 100 101 110 111
Right Record Source MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN
REV. B
-15-
AD1981B
Record Gain Register (Index 1Ch)
Reg No. Name 1Ch Record Gain D15 IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 LIM1 D8 LIM0 D7 D6 D5 X D4 X D3 D2 D1 RIM1 D0 Default
RM* X
RIM3 RIM2
RIM0 8000h
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VI for examples.
RIM[3:0] RM LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Input Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table VI. Settings for Record Gain Register
Reg. 76h
Control Bits Record Gain (1Ch) Left Channel Input Mixer D[11:8] Right Channel Input Mixer D[3:0] D7* x x x 1 0 1 WRITE 1111 0000 xxxx xxxx 1111 xxxx READBACK Function 1111 0000 xxxx xxxx 1111 xxxx 22.5 dB Gain 0 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted 22.5 dB Gain - dB Gain, Right Muted
MSPLT* D15 WRITE 0 0 0 1 1 1 0 0 1 0 1 1 1111 0000 xxxx 1111 xxxx xxxx
READBACK 1111 0000 xxxx 1111 xxxx xxxx
Function 22.5 dB Gain 0 dB Gain - dB Gain, Muted 22.5 dB Gain - dB Gain, Left Only Muted - dB Gain, Left Muted
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. x is a wild card and has no effect on the value.
General-Purpose Register (Index 20h)
Reg No. Name 20h General-Purpose D15 X D14 X D13 X D12 X D11 X D10 X D9 MIX D8 MS D7 LPBK D6 X D5 X D4 X D3 X D2 X D1 X D0 X Default 0000h
This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed to be reserved.
LPBK
Loopback Control. ADC/DAC Digital Loopback Mode. 0 = No Loopback (Default). 1 = Loopback PCM Digital Data from ADC Output to DAC. MIC Select. Selects mono MIC input. 0 = Select MIC1. 1 = Select MIC2. See 2CMIC bit in Register 76h to enable stereo microphone recording. Mono Output Select. Selects mono output audio source. 0 = Mixer mono output (reset default). 1 = MIC1 channel.
MS
MIX
-16-
REV. B
AD1981B
Power-Down Control/Status Register (Index 26h)
Reg No. Name 26h Power-Down Ctrl/Stat D15 EAPD D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 D9 PR2 PR1 D8 D7 D6 X D5 X D4 X D3 REF D2 ANL D1 DAC D0 ADC Default 000Xh
PR0 X
The ready bits are read-only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1981B subsections. If the bit is a 1, that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved.
ADC DAC ANL REF PR [6:0]
ADC Sections Ready to Transmit Data. DAC Sections Ready to Accept Data. Analog Amplifiers, Attenuators, and Mixers Ready. Voltage References, VREF, and VREFOUT up to Nominal Level. Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.
EAPD
External Audio Power-Down Control. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default). EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off. Set Bits PR0 PR1 PR1, PR2 PR0, PR1, PR3 PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5, PR6 PR6
Extended Audio ID Register (Index 28h)
Power-Down State ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down (VREF and VREFOUT On) Analog Mixer Power-Down (VREF and VREFOUT Off) AC-Link Interface Power-Down Internal Clocks Disabled ADC and DAC Power-Down VREF Standby Mode Total Power-Down Headphone Amp Power-In Standby
PR [6:0] [000 0001] [000 0010] [000 0101] [000 1011] [001 000] [011 0011] [000 0011] [011 0111] [111 1111] [100 0000]
Reg No. Name
D15
D14
D13 D12 D11 X REVC1
D10 REVC0
D9 AMAP
D8 X
D7 X
D6 X
D5 DSA1
D4 DSA0
D3 D2 X
D1 D0 VRAS
Default X605h
28h Ext'd Audio ID IDC1 IDC0 X
SPDIF X
The Extended Audio ID Register identifies which extended audio features are supported. A nonzero Extended Audio ID value indicates that one or more of the extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved.
REV. B
-17-
AD1981B
VRAS SPDIF Variable Rate PCM Audio Support (Read-Only). This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported. SPDIF Support (Read-Only). This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed to be set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DAC Slot Assignments (Read/Write) (Reset Default = 00). 00 DACs 1, 2 = 3 and 4. 01 DACs 1, 2 = 7 and 8. 10 DACs 1, 2 = 6 and 9. 11 Reserved. Slot DAC Mappings Based on Codec ID (Read-Only). This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are supported. REVC[1,0] = 01 indicates codec is AC '97 revision 2.2 compliant (Read-Only). Indicates Codec Configuration (Read-Only). 00 = Primary. 01, 10, 11 = Secondary.
Extended Audio Status and Control Register (Index 2Ah)
Reg No. Name D15 D14 D13 X X D12 X D11 D10 X SPCV D9 X D8 X D7 X D6 X D5 D4 D3 D2 D1 D0 Default
DSA[1,0]
AMAP REVC[1,0] IDC[1:0]
2Ah Ext'd Audio Stat/Ctrl VFORCE
SPSA1 SPSA0 X
SPDIF X
VRA 0000h
All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control register is a read/write register that provides status and control of the extended audio features.
VRA
Variable Rate Audio (Read/Write). VRA = 0 sets fixed sample rate audio at 48 kHz (reset default). VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write). SPDIF = 1 enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF transmitter (default). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported). Validity Force Bit (Reset Default = 0). When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the V bit (D15) in Register 3Ah (SPDIF control register). VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid. VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid. VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
SPDIF
SPSA[1:0] SPCV
VFORCE
-18-
REV. B
AD1981B
AC '97 2.2 AMAP Compliant Default SPDIF Slot Assignments
Codec ID 00 00 00 01 01 10 10 11
Function 2-Ch Primary w/SPDIF 4-Ch Primary w/SPDIF 6-Ch Primary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF
SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4
SPSA = 01 7 and 8 (default) 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8
SPSA = 10 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9
SPSA = 11 10 and 11 10 and 11 10 and 11 (default) 10 and 11 (default) 10 and 11 (default) 10 and 11 (default)
PCM Front DAC Rate Register (Index 2Ch)
Reg No. Name 2Ch PCM Front DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If 0 is written to VRA, the sample rate is reset to 48k.
PCM ADC Rate Register (Index 32h)
Reg No. Name 32h PCM L/R ADC Rate
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If 0 is written to VRA, the sample rate is reset to 48k.
REV. B
-19-
AD1981B
SPDIF Control Register (Index 3Ah)
Reg No. Name 3Ah SPDIF Control D15 V D14 X D13 SPSR1 D12 SPSR0 D11 L D10 CC6 D9 D8 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 D2 D1 D0 Default
CC5 CC4
PRE COPY /AUD PRO 2000h
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
PRO /AUD COPY PRE CC[6:0] L SPSR[1:0]
Professional. 1 indicates professional use of channel status. 0 indicates consumer. Non-Audio. 1 indicates data is non-PCM format. 0 data is PCM. Copyright. 1 indicates copyright is asserted. 0 copyright is not asserted. Pre-Emphasis. 1 indicates filter pre-emphasis is 50 s/15 s. 0 pre-emphasis is none. Category Code. Programmed according to IEC standards, or as appropriate. Generation Level. Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate. SPSR[1:0] = 00 transmit sample rate = 44.1 kHz. SPSR[1:0] = 01 Reserved. SPSR[1:0] = 10 transmit sample rate = 48 kHz (reset default). SPSR[1:0] = 11 not supported. Validity. This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext'd Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid.
V
-20-
REV. B
AD1981B
EQ Control Register (Index 60h)
Reg No. Name D15 D14 MAD LBEN D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 D3 D2 D1 D0 Default
60h EQ CTRL EQM
SYM CHS
BCA5 BCA4 BCA3
BCA2 BCA1 BCA0 8080h
Register 60h is a read/write register that controls the equalizer functionality and data setup. This register also contains the Biquad and Coefficient Address pointer, which is used in conjunction with the EQ Data Register (78h) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the Symmetry bit to allow equal coefficients for left and right channels. All registers not shown and bits containing an X are assumed to be reserved.
BCA[5,0]
Biquad and Coefficient Address Pointer biquad 0 coef a0 BCA[5,0] = 011011 biquad 0 coef a1 BCA[5,0] = 011010 biquad 0 coef a2 BCA[5,0] = 011001 biquad 0 coef b1 BCA[5,0] = 011101 biquad 0 coef b2 BCA[5,0] = 011100 biquad 1 coef a0 BCA[5,0] = 100000 biquad 1 coef a1 BCA[5,0] = 011111 biquad 1 coef a2 BCA[5,0] = 011110 biquad 1 coef b1 BCA[5,0] = 100010 biquad 1 coef b2 BCA[5,0] = 100001 biquad 2 coef a0 BCA[5,0] = 100101 biquad 2 coef a1 BCA[5,0] = 100100 biquad 2 coef a2 BCA[5,0] = 100011 biquad 2 coef b1 BCA[5,0] = 100111 biquad 2 coef b2 BCA[5,0] = 100110 biquad 3 coef a0 BCA[5,0] = 101010 biquad 3 coef a1 BCA[5,0] = 101001 biquad 3 coef a2 BCA[5,0] = 101000 biquad 3 coef b1 BCA[5,0] = 101100 biquad 3 coef b2 BCA[5,0] = 101011 biquad 4 coef a0 BCA[5,0] = 101111 biquad 4 coef a1 BCA[5,0] = 101110 biquad 4 coef a2 BCA[5,0] = 101101 biquad 4 coef b1 BCA[5,0] = 110001 biquad 4 coef b2 BCA[5,0] = 110000 biquad 5 coef a0 BCA[5,0] = 110100 biquad 5 coef a1 BCA[5,0] = 110011 biquad 5 coef a2 BCA[5,0] = 110010 biquad 5 coef b1 BCA[5,0] = 110110 biquad 5 coef b2 BCA[5,0] = 110101 biquad 6 coef a0 BCA[5,0] = 111001 biquad 6 coef a1 BCA[5,0] = 111000 biquad 6 coef a2 BCA[5,0] = 110111 biquad 6 coef b1 BCA[5,0] = 111011 biquad 6 coef b2 BCA[5,0] = 111010
CHS
Channel Select. CHS = 0 selects left channel coefficients data block. CHS = 1 selects right channel coefficients data block. Symmetry. When set to 1, this bit indicates that the left and right channel coefficients are equal. This shortens the coefficients' setup sequence since only the left channel coefficients need to be addressed and set up (the right channel coefficients are fetched from the left channel memory). Mixer ADC Loopback Enable. Enables mixer ADC data to be summed into PCM stream. 0 = No loopback allowed (default). 1 = Enable loopback. Equalizer Mute. When set to 1, this bit disables the equalizer function (allows all data to pass through). The reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set. -21-
SYM
MAD LBEN EQM REV. B
AD1981B
EQ Data Register (Index 62h)
Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA bits in the EQ CNTRL Register (60h). Data will be written to memory only if the EQM bit (Register 60h, Bit 15) is asserted.
CFD[15:0]
Coefficient Data. The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is the MSB, and the CFD0 bit is the LSB.
Mixer ADC, Input Gain Register (Index 64h)
Reg No. Name 64h Mixer Volume
D15
D14
D13 X
D12 X
D11
D10
D9
D8
D7
D6
D5 X
D4 X
D3
D2
D1
D0
Default
MXM X
LMG3 LMG2
LMG1 LMG0 RM* X
RMG3 RMG2 RMG1
RMG0 8000h
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples.
RMG[3:0] RM LMG[3:0] MXM
Right Mixer Gain Control. This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The least significant bit represents 1.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MXM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left Mixer Gain Control. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The least significant bit represents 1.5 dB. Mixer Gain Register Mute. 0 = Unmuted. 1 = Muted (reset default).
Table VII. Settings for Mixer ADC, Input Gain
Reg. 76h
Control Bits Mixer ADC, Input Gain (64h) Left Channel Mixer Gain D[11:8] Right Channel Mixer Gain D[3:0] D7* x x x 1 WRITE READBACK Function 1111 0000 xxxx xxxx 1111 xxxx 1111 0000 xxxx xxxx 1111 xxxx 22.5 dB Gain 0 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted 22.5 dB Gain - dB Gain, Right Muted
MSPLT* D15 WRITE READBACK 0 0 0 1 1 1 0 0 1 0 1 1 1111 0000 xxxx 1111 xxxx xxxx 1111 0000 xxxx 1111 xxxx xxxx
Function 22.5 dB Gain 0 dB Gain - dB Gain, Muted 22.5 dB Gain
- dB Gain, Left Only Muted 0 - dB Gain, Left Muted 1
*For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. x is a wild card and has no effect on the value.
-22-
REV. B
AD1981B
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Reg No. Name 72h Jack Sense D15 D14 X X D13 D12 X JS MT2 D11 JS MT1 D10 JS MT0 D9 JS1 EQB D8 JS0 EQB D7 JS1 TMR D6 JS0 TMR D5 JS1 MD D4 JS0 MD D3 JS1 ST D2 JS0 ST D1 JS1 INT D0 JS0 INT Default 0000h
All register bits are read/write except for JS0ST and JS1ST, which are read only. All registers not shown and bits containing an X are assumed to be reserved.
JS0INT
Indicates Pin JS0 Has Generated an Interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR should clear this bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also note that the actual interrupt implementation is selected by the INTS bit (Register 76h). It is also possible to generate a software system interrupt by writing a 1 to this bit. Indicates Pin JS1 Has Generated an Interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this bit by writing a 0 to it. See JS0INT description for additional details. JS0 State. This bit always reports the logic state of JS0 pin. JS1 State. This bit always reports the logic state of JS1 pin. JS0 Mode. This bit selects the operation mode for the JS0 pin. 0 = Jack Sense mode (default). 1 = Interrupt mode. JS1 Mode. This bit selects the operation mode for the JS1 pin. 0 = Jack Sense mode (default). 1 = Interrupt mode. JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized. JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized. JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will cause the EQ to be bypassed. JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 will cause the EQ to be bypassed. JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table VIII).
JS1INT JS0ST JS1ST JS0MD
JS1MD
JS0TMR JS1TMR JS0EQB JS1EQB JSMT[2,0]
REV. B
-23-
AD1981B
Table VIII. Jack Sense Mute Select-JSMT [2:0]
JS1 JS0 REF HEADPHONE LINE OUT 0 1 2 3 4 5 6 7 8 OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0)
H.P. JSMT2 JSMT1 JSMT0 OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE
LINE OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE
MONO OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
NOTES JS0 and JS1 Ignored.
JS0 No Mute Action; JS1 Mutes Line_Out.
JS0 No Mute Action; JS1 Mutes Mono and Line_Out.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0)
IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0)
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FMUTE ACTIVE ACTIVE ** ** ** ** FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE
ACTIVE FMUTE FMUTE ** ** ** ** FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE
ACTIVE FMUTE FMUTE ** ** ** ** ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE JS0 Mutes Mono; JS1 Mutes Mono and Line_Out. JS0 Mutes Mono; JS1 Mutes Line_Out. ** Reserved
JS0 Mutes Mono; JS1 No Mute Action.
25 26 27 28 29 30 31
OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1)
IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1)
1 1 1 1 1 1 1
1 1 1 1 1 1 1
0 0 0 1 1 1 1
FMUTE ACTIVE ACTIVE ** ** ** **
ACTIVE FMUTE FMUTE ** ** ** **
FMUTE FMUTE FMUTE ** ** ** ** ** Reserved
FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing plugged into the jack and therefore the JS status is low (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is high (via the codec JS internal pull-up).
-24-
REV. B
AD1981B
Serial Configuration Register (Index 74h)
Reg No. Name D15
D14
D13
D12
D11 D10 D9 D8 X X
D7 D6 D5 D4 X X
D3 D2
D1
D0
Default
74h Serial SLOT16 REGM2 REGM1 REGM0 X Configuration
CHEN X
INTS X
SPAL SPDZ SPLNK 7001h
This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.
SPLNK
SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the same data requests (reset default). SPDIF DACZ. 0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO underruns. SPDIF ADC Loop-Around. 0 = SPDIF transmitter is connected to the ac-link stream (reset default). 1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link. Interrupt Mode Select. This bit selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (modem interrupt). 1 = Slot 6 valid bit (MIC ADC interrupt). Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin. Master Codec Register Mask. Slave 1 Codec Register Mask. Slave 2 Codec Register Mask. Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing.
Miscellaneous Control Bit Register (Index 76h)
SPDZ
SPAL
INTS
CHEN
REGM0 REGM1 REGM2 SLOT16
Reg No. Name
D15
D14 D13
D12
D11
D10 D9
D8 D7
D6
D5 D4
D3
D2
D1
D0
Default
76th Misc DACZ X Control Bits
MSPLT LODIS DAM X
FMXE X
MADPD 2CMIC X
MADST VREFH VREFD MBG1 MBG0 0000h
All registers not shown and bits containing an X are assumed to be reserved.
MBG[1:0]
MIC Boost Gain Change Register. These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Note: This gain setting takes affect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise, the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default). 01 = 10 dB gain. 10 = 30 dB gain. 11 = Reserved. VREFOUT Disable. Disables VREFOUT, placing it into High Z Out mode. Note that this bit overrides the VREFH bit selection (see below). 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into High Z Out mode. VREFOUT High. Changes VREFOUT from 2.25 V to 3.70 V for MIC bias applications. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 3.70 V output.
VREFD
VREFH
REV. B
-25-
AD1981B
MADST Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels). 0 = Mixer ADC not ready. 1 = Mixer ADC ready. 2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h. 0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector's left and right MIC channels as well as to the mixer (reset default). 1 = MIC1 is routed to the record selector's left MIC channel and MIC2 is routed to the record selector's right MIC channel. Note that in this mode, the MS bit should be set low and MIC1 can still be enabled into the mixer. Mixer ADC Power Down. Controls power down for mixer digitizing ADC. 0 = Mixer ADC is powered on (default). 1 = Mixer ADC is powered down. Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches. 0 = Front DAC outputs are allowed to sum into the mixer (reset default). 1 = Front DAC outputs are muted into the mixer (blocked). Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output. LINE_OUT Disable. Disables the LINE_OUT pins (L/R), placing them into High Z mode so that the assigned output audio jack can be shared for input function (or other function). 0 = LINE_OUT pins have normal audio drive capability (reset default). 1 = LINE_OUT pins are placed into High Z mode. Mute Split. Allows separate mute control bits for Master, Headphone, LINE_IN, CD, AUX, and PCM volume control registers as well as record gain register. 0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default). 1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute. DAC Zero-Fill. Determines DAC data fill under starved conditions. 0 = DAC data is repeated when DACs are starved for data (reset default). 1 = DAC is zero-filled when DACs are starved for data.
Vendor ID Register (Index 7Ch-7Eh)
2CMIC
MADPD
FMXE
DAM LODIS
MSPLT
DACZ
Reg No. Name
D15
D14 D13 F6 F5
D12 F4
D11 F3
D10 F2
D9 F1
D8 F0
D7 S7
D6 S6
D5 S5
D4 S4
D3 S3
D2 D1 D0 Default S2 S1 S0 4144h
7Ch Vendor ID1 F7
S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D.
Reg No. Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 T5 T4 T3 T2
D6
D5
D4
D3
D2
D1
D0
Default
7Eh Vendor ID2 T7 T6
T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h
T[7:0] This register is ASCII encoded to S. REV[7:0] Vendor specific revision number: The AD1981B assigns 74h to this field.
Table IX. Codec ID and External Clock Selection Table
ID1 1 1 0 0
ID0 1 0 1 0
Codec ID (00) Primary (01) Secondary (00) Primary (00) Primary
Codec Clocking Source 24.576 MHz 12.288 MHz 48.000 MHz 14.31818 MHz (Local Xtal or External into XTL_IN) (External into BIT_CLK) (External into XTL_IN) (External into XTL_IN)
Note that internally, the ID pins have weak pull-ups and are inverted.
-26-
REV. B
AD1981B
OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48)
Dimensions shown in millimeters
0.75 0.60 0.45
1.60 MAX
48 1
9.00 BSC SQ
37 36
1.45 1.40 1.35
10 6 2
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
PIN 1
TOP VIEW
(PINS DOWN)
7.00 BSC SQ
VIEW A
12 13 24 25
0.15 0.05
SEATING PLANE
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. B
-27-
AD1981B Revision History
Location 6/03--Data Sheet changed from REV. A to REV. B. Page
Changes to TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/03--Data Sheet changed from REV. 0 to REV. A.
C03091-0-6/03(B)
Changes to ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to Figure 6 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
-28-
REV. B

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